AMD Strix Point engineering sample underwhelms in early Geekbench 6 results

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By Aaron Klotz
published

Clock speeds are holding back this latest engineering sample's performance.

Ryzen Mobile Processor
(Image credit: AMD)

An engineering sample of a Zen 5 Strix Point CPU has made an appearance on Geekbench 6. Discovered by @haurkaze5719 on X (formerly Twitter), the CPU features 12 cores, 16MB of L3 cache, and a 28W TDP. Strix Point is the codename for AMD's upcoming Zen 5-based Ryzen mobile processors.

Unfortunately, the benchmark results on Geekbench 6 don't show us the chip's full potential. In fact, its performance is drastically lower than today's Ryzen 8000 mobile processors, likely due to the fact that it's an engineering sample. The CPU only achieves a multi-core score of 8,016 points and a single-core score of 1,217 points. By comparison, a six-core Ryzen 5 8640U utilizing AMD's Zen 4 architecture archives well over 8,500 points in the multi-core test and over 2,000 points in the single-core test, in most cases.

The Strix Point sample's slow performance is caused by the chip's extremely slow clock speeds —  the engineering sample was running at just 1.4GHz throughout the whole test.

That said, this new engineering sample reveals that AMD is currently working on Zen 5-based mobile solutions. In fact, the sample has the same FP8 nomenclature that we saw on a shipment of CPUs one month ago. So it's been around for some time.

The core CPU specs align with speculation that Strix Point will feature upgraded core counts compared to AMD's current Ryzen 7040 and 8040 series mobile processors. There's a chance Strix Point could feature 12 P-cores, but it's more likely that it will use a mixture of P-cores and Zen 5c E-cores to hit the 12-core target. Unfortunately, it appears the L3 cache and L2 cache are still unchanged, coming in at 16MB and 1MB respectively. We have yet to see how this will impact performance, but it appears Zen 5 will be getting most of its performance prowess from its Zen 5 cores alone.

What we do know, aside from the Zen 5 aspect of the chip, is that Strix Point will come with a more potent RDNA 3+ integrated graphics unit, as well as a significantly more powerful XDNA 2 NPU. AMD confirmed that XDNA 2 will offer twice the performance of its predecessor, translating to over 70 TOPS of performance — well above Microsoft's 40 TOPS requirement for AI PCs.

Zen 5 is expected to feature a 15% IPC improvement just from the architecture itself. With the addition of 12 Zen 5 cores on top of the GPU and NPU improvements, Strix Point is shaping up to be a significant upgrade over AMD's existing low-power Ryzen 8000 series CPUs.

Aaron Klotz
Aaron Klotz
Freelance News Writer

Aaron Klotz is a freelance writer for Tom’s Hardware US, covering news topics related to computer hardware such as CPUs, and graphics cards.

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31 Comments Comment from the forums
  • Metal Messiah.
    There's a chance Strix Point could feature 12 P-cores, but it's more likely that it will use a mixture of P-cores and Zen 5c E-cores to hit the 12-core target.

    Since when does AMD has P and E core configuration like Intel ?

    Zen 5c "dense" core is just a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets.
    Reply
  • Metal Messiah.
    AMD confirmed that XDNA 2 will offer twice the performance of its predecessor, translating to over 70 TOPS of performance — well above Microsoft's 40 TOPS requirement for AI PCs.

    70 TOPS ? Wrong. You must be joking. It's thrice the performance improvement btw, not twice.

    The "TOTAL" TOPS value is a different story though.
    As per AMD, XDNA 2 NPU is expected to introduce an over 3 times improvement in performance over the first generation XDNA NPU powering the Ryzen 7040 series "Phoenix" processor.

    "Phoenix" offers 10 TOPS of NPU performance, so if AMD mentions an "over 3 times" performance improvement, this would put this figure at roughly 32 TOPS for "Strix Point."

    Also, 8040 "Hawk Point" APUs offer up to 16 TOPs of performance, a 3x improvement with Ryzen "Strix Point" APUs means that we could be looking at up to 48 TOPs of AI performance, give or take.

    The core CPU specs align with speculation that Strix Point will feature upgraded core counts compared to AMD's current Ryzen 7040 and 8040 series mobile processors

    Not entirely correct. The core counts with Strix Point won't see a VERY huge upgrade though. Do you make up your own story while writing articles?

    Btw, these are Geekbench 5 entries, and not GB 6 as the article mentions.
    Reply
  • usertests
    16 MB L3 is wrong. It's probably detecting it wrong because it's dual-CCX this time around.

    4x Zen 5 cores with 16 MB L3
    8x Zen 5c cores with 8 MB L3

    Metal Messiah. said:
    Since when does AMD has P and E core configuration like Intel ?

    Zen 5c "dense" core is just a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets.
    It might be unfair to call 'C' cores "E-cores", but they do fill similar roles. Greater multi-threaded performance per die area, greater power efficiency in part from limiting the clocks (it's more complicated than that).

    Metal Messiah. said:
    Also, 8040 "Hawk Point" APUs offer up to 16 TOPs of performance, a 3x improvement with Ryzen "Strix Point" APUs means that we could be looking at up to 48 TOPs of AI performance.
    Yup, should be at least 45 TOPS.

    The NPU being capable of outperforming the iGPU+CPU would be a neat trick.

    Metal Messiah. said:
    Not entirely correct. The core counts with Strix Point won't see any huge upgrade.
    50% increase in core/thread count (caveats not mentioned).
    Reply
  • Metal Messiah.
    usertests said:
    16 MB L3 is wrong. It's probably detecting it wrong because it's dual-CCX this time around.

    4x Zen 5 cores with 16 MB L3
    8x Zen 5c cores with 8 MB L3

    Yeah correct, the chip itself might feature a total of 24 MB L3 cache, and 12 MB of L2 cache in total.

    1782964481322107229View: https://twitter.com/Kepler_L2/status/1782964481322107229

    BTW, one more entry was also spotted, running on the Birman Plus-STX reference platform. It says 2 processors here though ! Has the same OPN ID of "100-000000994-14_N".

    https://i.imgur.com/b5Kyxkp.png
    Reply
  • mawkzin
    AMD used the NPU + GPU + CPU to address the total 33 AI TOPS for the 7040 Series, the NPU can produce 10 TOPS and when combined with the CPU+GPU it can achieve the 33 TOPS, so you'll have the "3 x 10 TOPS from the XDNA 2" + "the upgraded RDNA 3+ (16 CU vs previous 12 CU)" + "the new 12 C Zen5 CPU (+50% threads over zen4 APUs)" to achieve 60~70 TOPS in total.
    Reply
  • NinoPino
    The single thread score is very good for a 1.4Ghz CPU without boost.
    It is a +110% referred to a 8640U (3.5/4.9 Ghz).
    Something wrong here ?

    Strix Point single-core of 1,217 points.
    Ryzen 5 8640U over 2,000 points in the single-core

    1217 : 1.4 = x : 3.5 -> 3042 -> +50%
    1217 : 1.4 = x : 4.9 -> 4260 -> +110%
    Reply
  • setx
    usertests said:
    It might be unfair to call 'C' cores "E-cores", but they do fill similar roles.
    They are not. E-cores role is to cripple P-cores and create all kinds of headaches for developers who want to optimize their software. Basically, it's an insult of a core.

    The 'c' should be called something like 'dense cores' since they are exactly the same as 'normal cores' from software point of view.
    Reply
  • watzupken
    I guess the purpose of these C cores are to act as more efficient cores due to some minor cutbacks. Ultimately they are still on the same chip architecture. Intel's approach of E-cores to me are a bunch of cheaper cores that they handily spam to boost their multithread numbers. Overall I think AMD's approach likely causes less issues. Assuming an app utilizes the wrong core, the performance penalty is not as significant. And if you read Anandtech's review on Meteor Lake, those Intel E-cores have very high latency which is not a good sign.
    Reply
  • TerryLaze
    setx said:
    They are not. E-cores role is to cripple P-cores and create all kinds of headaches for developers who want to optimize their software. Basically, it's an insult of a core.

    The 'c' should be called something like 'dense cores' since they are exactly the same as 'normal cores' from software point of view.
    No it creates headaches for devs that don't want to optimize and only do the least amount of work, if they even do that.

    And the same will be true for the c cores, the c cores will introduce a lot of sync issues in games and the devs will drag all the cores down to the c core speeds to avoid these sync issues or only run games on full cores losing a lot of performance, or they won't even do that and a lot of games will just have issues until you shut down the c cores or set affinity to only the normal cores.

    For apps it's a lot less of an issue since multithreaded apps can just launch different workloads for any type of core there is. Also intel is working on avx10 which will do that automatically for avx.
    Reply
  • NinoPino
    TerryLaze said:
    And the same will be true for the c cores, the c cores will introduce a lot of sync issues in games and the devs will drag all the cores down to the c core speeds to avoid these sync issues or only run games on full cores losing a lot of performance, or they won't even do that and a lot of games will just have issues until you shut down the c cores or set affinity to only the normal cores.
    I totally disagree with you here. There are sync issues with threads in any case, also if you have exactly the same core, same clock and same workload. Programs runs under a multitasking OS and you have program flow perturbation due to external peripherals and interrupts for example. Add that you have also variable frequency and not all cores have the same max clock...
    TerryLaze said:
    For apps it's a lot less of an issue since multithreaded apps can just launch different workloads for any type of core there is.
    True, but with a programming overhead.
    In case of cores with different instruction set, the effort is not trivial.
    Not only programmer must produce a code that spawn threads with different codepaths but also all frameworks and libraries involved need to manage such cases.
    TerryLaze said:
    Also intel is working on avx10 which will do that automatically for avx.
    For me avx10 is intended to put some order in the chaos and I do not see how avx10 can automatically solve the problem of "Intel's e-cores".
    Reply